姓名：杨晨
职称：副教授，博士生导师
研究方向：数字SoC设计、可重构计算、AI加速器与安全、新型密码芯片、通信和网络协议卸载
邮箱：chyang00@xjtu.edu.cn
个人主页：http://gr.xjtu.edu.cn/web/chyang00
1、个人简介：
杨晨，陕西西安人，在清华大学取得电子科学与技术专业学士、硕士和博士学位，曾在威盛电子(中国)有限公司从事多媒体SoC芯片的设计研发工作。2016年进入永利集团304am登录工作，目前担任副教授、博士生导师。
2、研究领域或方向：
1） 超大规模数字SoC系统(System-on-Chip)的VLSI设计
2） 动态可重构计算芯片(Dynamically Reconfigurable Chip)的架构研究
3） 高带宽片上存储(On-chip Memory)结构和高速缓存(Cache)管理技术研究
4） 面向各类型神经网络算法(Neural Network)的可重构AI加速器研究
5） 存内计算芯片的编译技术(Compiler)研究及架构建模(Simulator)优化
6） 基于深度学习(Deep Learning)的智能应用与系统研究
7） 全同态密码算法(Fully Homomorphic Encryption)处理器设计
8） 后量子密码(Post-Quantum Cryptography)芯片设计
9） 面向通信算法(Communication)的高能效高面效计算架构研究
10） 面向网络协议(Networking)的高性能硬件卸载引擎设计
3、正在或曾经承担的科研项目：
主持科研项目17项：
1）科技部，国家重点研发计划项目子课题，“后量子密码芯片的敏捷公钥密码计算通路设计”，在研，主持
2）国家自然科学基金委员会，面上项目，“面向可重构神经网络加速器的硬件安全防护机制研究”，在研，主持
3）中国计算机学会，CCF-蚂蚁隐私计算专项科研基金项目， “基于CKKS和TFHE切换技术的密文AI推理加速器设计”，在研，主持
4）兴唐通信科技有限公司，横向课题，“FPGA高速处理定制技术”，在研，主持
5）航天九院第771研究所，横向课题，“基于混合位宽的神经网络加速器设计”，在研，主持
6）航空科学基金，人工智能专项，“基于分支网络的高效能无人机目标识别与检测系统研究”，在研，主持
7）上海闪易半导体有限公司，横向课题，“存内计算芯片的多核架构研究与编译器设计”，在研，主持
8）北京升宇科技有限公司，横向课题，“数字电路全流程设计的抗辐射加固技术”，在研，主持
9）国家自然科学基金委员会，青年基金项目，“动态可重构处理器片上缓存管理关键技术研究”，已结题，主持
10）中国博士后科学基金，一等资助项目，“基于深度学习的高能效可重构智能芯片关键技术研究”，已结题，主持
11）陕西省博士后科研项目，面上项目，“动态可重构神经网络加速器处理单元设计与VLSI实现”，已结题，主持
12）中国计算机学会，CCF-百度松果基金项目，“面向动态可重构神经网络加速器的软硬协同一体的轻量化编译器设计”，已结题，主持
13）华为技术有限公司，横向课题，“算子归一和硬件架构联合设计”，已结题，主持
14）航天九院第771研究所，创新基金项目，“极低功耗神经网络加速器设计方法研究”，已结题，主持
15）上海闪易半导体有限公司，横向课题，“面向存内计算芯片的编译器研究”， 已结题，主持
16）永利集团304am登录，自由探索与创新项目，“高效能融合多种神经网络运算的动态可重构处理器研究”，已结题，主持
17）永利集团304am登录，本科教学改革研究项目，“《计算机原理与嵌入式系统》课程产教融合协同创新育人模式研究”，已结题，主持
作为骨干研究人员参加科研项目6项：
1）国家自然科学基金委员会，面上项目，“无人系统自主定位及环境建模的计算优化与软硬件协同设计”，在研，参加
2）广东省科技厅，重点领域研发计划“新一代人工智能”重大科技专项，“工业级多模智能感知系统关键技术与边云协同应用”，在研，参加
3）科技部，国家重点研发计划项目子课题，“压电式微滴喷射阵列打印头智能驱动芯片及模块设计与开发”，已结题，参加
4）科技部，“十二五”863重点项目子课题，“可重构处理器架构研究、内核设计、芯片研发”，已结题，参加
5）科技部，“十一五”863重点项目子课题，“可重构PE和PE阵列的架构设计和IP核实现”，已结题，参加
6）国家自然科学基金委员会，青年基金项目，“新型复数算术运算单元设计与VLSI实现”，已结题，参加
4、获奖情况及科研成果：
获奖情况：
1）2024年，第八届“全国大学生集成电路创新创业大赛” 优秀指导教师
2）2023年，第七届“全国大学生集成电路创新创业大赛” 优秀指导教师
3）2022年，第十七届“中国研究生电子设计竞赛”优秀指导教师
4）2022年，第六届“全国大学生集成电路创新创业大赛” 优秀指导教师
5）2021年，第五届“全国大学生集成电路创新创业大赛” 优秀指导教师
6）2020年，第四届“全国大学生集成电路创新创业大赛” 优秀指导教师
7）2020年，永利集团304am登录（2017级本科）优秀专业实习队指导教师
8）2019年，第三届“全国大学生集成电路创新创业大赛”优秀指导教师
9）2019年，永利集团304am登录（2016级本科）优秀专业实习队指导教师
10）2018年，第二届“全国大学生集成电路创新创业大赛”优秀指导教师
11）2018年，永利集团304am登录（2015级本科）优秀专业实习队指导教师
12） 2017年，第一届“全国大学生集成电路创新创业大赛”优秀指导教师
13） 2017年，永利集团304am登录（2014级本科）优秀专业实习队指导教师
14） 2016年，清华大学“启航奖”个人金奖
代表论文（通讯作者加*）：
（1）期刊论文：
[1] Jianfei Wang, Chen Yang*, et al., “A Reconfigurable and Area-Efficient Polynomial Multiplier using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024, in press.
[2] Yizhou Wang, Yishuo Meng, Jiaxing Wang, Chen Yang*, “LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy using Long-Short Term Memory” [J], Big Data and Cognitive Computing, 2024, in press.
[3] Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang*, “A Scalable and Efficient NTT/INTT Architecture using Group-based Pairwise Memory Access and Fast Inter-Stage Reordering” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, in press.
[4] Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang, Jia Hou, Zhijie Lin, Chen Yang*, “A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024, in press.
[5] Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang*, “An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture using Least-Positive Form and Winograd Fast Algorithm” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024, in press.
[6] Wenzheng He, Zikuo Lu, Xin Liu, Ziwei Xu, Jingshuo Zhang, Chen Yang*, Li Geng*, “A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024, in press.
[7] Jianfei Wang, Chen Yang*, et al., “A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024, in press.
[8] Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang*, “A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-based Cryptography” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024, in press.
[9] Zichu Liu, Jia Hou, Jianfei Wang, Chen Yang*, “A Novel Two-level Protection Scheme Against Hardware Trojans on a Reconfigurable CNN Accelerator” [J], Cryptography, 2024, 8(3): 34.
[10] Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang*, “ALSCA: A Large-Scale Sparse CNN Accelerator using Position-first Dataflow and Input Channel Merging Approach” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024, 71(7): 3473-3477.
[11] Jia Hou, Zichu Liu, Zepeng Yang, Chen Yang*, “Hardware Trojan Attacks on the Reconfigurable Interconnections of FPGA-Based CNN Accelerators and a PUF-based Countermeasure Detection Technique” [J], Micromachines, 2024, 15(1): 149.
[12] Fahong Zhang, Chen Yang*, et al., “An Efficient and Scalable FHE-based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm” [J], IEEE Transactions on Information Forensics & Security (TIFS), 2024, 19: 2258-2272.
[13] Siwei Xiang, Xianxian Lv, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang*, “WRA-MF: A Bit-Level Convolutional-Weight-Decomposition Approach to Improve Parallel Computing Efficiency for Winograd-Based CNN Acceleration” [J], Electronics, 2023, 12(24): 4943.
[14] Jianfei Wang, Chen Yang*, et al., “A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA using a Novel Winograd-Based Architecture” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024, 71(4): 2344-2348.
[15] Jianfei Wang, Chen Yang*, et al., “A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography using a Novel Winograd-Schoolbook Algorithm” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024, 71(1): 359-372.
[16] Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang*, “POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection” [J], Information, 2023, 14(11): 604.
[17] Chen Yang, Yishuo Meng, et al., “WRA-SS: A High-Performance Accelerator Integrating Winograd with Structured Sparsity for Convolutional Neural Networks” [J], IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2024, 32(1): 164-177.
[18] Chen Yang, Yaoyao Yang, et al., “Flexible and Efficient Convolutional Acceleration on Unified Hardware using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units” [J], IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024, 43(3): 919-932.
[19] Yishuo Meng, Chen Yang*, et al., “An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(10): 1537-1550.
[20] Chen Yang, Junfeng Wu, et al., “A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT with Twiddle Factor Compression and Conflict-Free Access” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(10): 1472-1485.
[21] Yifan Gong, Jinshuo Zhang, Xin Liu, Jialin Li, Ying Lei, Zhe Zhang, Chen Yang*, Li Geng*, “A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2023, 70(12): 4914-4927.
[22] Jianfei Wang, Chen Yang*, et al., “TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier over Rings using a Novel Compressed Postprocessing Algorithm” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(8): 1153-1166.
[23] Yang Su, Bailong Yang, Jianfei Wang, Fahong Zhang, Chen Yang*, “Reconfigurable multi-core array architecture and mapping method for RNS-based homomophic encryption” [J], AEU - International Journal of Electronics and Communications (AEUE), 2023, 161(154562): 1-16.
[24] Chen Yang, Yishuo Meng, et al., “A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter- Convolutional/Pooling Layers” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30(12): 1902-1915.
[25] Chen Yang, Kai‑Bo Huo, et al., “DRGN: A Dynamically Reconfigurable Accelerator for Graph Neural Networks” [J], Journal of Ambient Intelligence and Humanized Computing (AIHC), 2022, 2022(9): 1-16.
[26] Chen Yang, Jia Hou, et al., “RNA: A Flexible and Efficient Accelerator based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks” [J], Journal of Circuits, Systems, and Computers (JCSC), 2022, 31(16): 2250289.
[27] Yang Su, Bailong Yang, Chen Yang*, et al., “A Highly Unified Reconfigurable Multicore Architecture to Speedup NTT/INTT for Homomorphic Polynomial Multiplication” [J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30(8): 993-1006.
[28] Yang Su, Bailong Yang, Chen Yang*, et al., “ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2022, 69(7): 2857-2870.
[29] Chen Yang, Qi Chen, et al., “SDF-SLAM: A Deep Learning based Highly Accurate SLAM using Monocular Camera aiming at Indoor Map Reconstruction with Semantic and Depth Fusion” [J], IEEE ACCESS, 2022, 10: 10259-10272.
[30] Chen Yang, Jingyu Zhang, et al., “UL-CNN: An Ultra-Lightweight Convolutional Neural Network aiming at Flash-based Computing-In-Memory Architecture for Pedestrian Recognition” [J], Journal of Circuits, Systems, and Computers (JCSC), 2021, 30(2): 2150022.
[31] Yang Su, Bai‑Long Yang, Chen Yang*, et al., “FPGA-based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption” [J], IEEE Access, 2020, 8: 168008-168025.
[32] Yang Su, Bai‑Long Yang, Chen Yang*, et al., “High-Flexible Hardware and Instruction of Composite Galois Field Multiplication Targeted at Symmetric Crypto Processor” [J], Journal of Ambient Intelligence and Humanized Computing (AIHC), 2020, 9(2): 1-17.
[33] Chen Yang, Yizhou Wang, et al., “A Stride-based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2020, 67(9): 3007-3020.
[34] Chen Yang, Yizhou Wang, et al., “WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks” [J], IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2019, 66(9): 3480-3493.
[35] Leibo Liu, Chen Yang*, et al., “CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance” [J], IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018, 37(6): 1171-1184.
[36] Leibo Liu, Zhaoshi Li, Chen Yang*, et al., “HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing” [J], IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2018, 65(3): 381-385.
[37] Chen Yang, Leibo Liu, et al., “CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays” [J], IEEE Transactions on Parallel and Distributed Systems (TPDS), 2017, 28(1): 29-43.
[38] Chen Yang, Leibo Liu, et al., “Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array” [J], Journal of Circuits, Systems, and Computers (JCSC), 2015, 24(03): 1550043.
[39] Chen Yang, Leibo Liu, et al., “Efficient and Flexible Memory Architecture to Alleviate Data and Context Bandwidth Bottlenecks of Coarse-Grained Reconfigurable Array” [J], Science of China F: Physics, Mechanics & Astronomy, 2014, 57(12): 2214–2227.
（2）会议论文：
[40] Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang*, “Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data” [C], Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASP-DAC), 2025, accepted.
[41] Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang*, “An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method” [C], Proceedings of the 6th IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2023: 1-2.
[42] Bokai Zeng, Chen Yang*, et al., “A Performance-driven Neural Network Compiler for Multi-core Computing-In-Memory Accelerator” [C], Proceedings of the IEEE 15th International Conference on ASIC (ASICON), 2023: 1-4.
[43] Zepeng Yang, Chen Yang*, et al., “An Acceleration Architecture of Polynomial Multiplication based on NTT for CKKS Homomorphic Evaluation” [C], Proceedings of the 8th International Conference on Integrated Circuits and Microsystems (ICICM), 2023: 1-5.
[44] Xin Liu, Yishuo Meng, Zhe Zhang, Jialin Li, Yifan Gong, Ying Lei, Chen Yang, Li Geng*, “Efficient Bicubic Interpolation Architecture for RGB Image Data Stream” [C], Proceedings of the 6th International Conference on Electronics Technology (ICET), 2023: 1356-1361.
[45] Chen Yang, Yawei Wang, et al., “CIMAX-Compiler: An End-to-End ANN Compiler for Heterogeneous Computing-In-Memory Platform” [C], Proceedings of the 6th World Conference on Computing and Communication Technologies (WCCCT), 2023: 1-5.
[46] Jialin Li, Liangji Zhang, Xuewei Shen, Yifan Gong, Ying Lei, Chen Yang, Li Geng, “A Hardware Architecture of Feature Extraction for Real-Time Visual SLAM” [C], Proceedings of the 48th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2022: 1-6.
[47] Chen Yang, Yishuo Meng, et al., “A High-performance Hardware Accelerator using a Fusion Approach of Convolution and Pooling” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2022: 1-3.
[48] Chen Yang, Fahong Zhang, et al., “A Multiplication-Free FPGA Implementation of Multiple RLWE Encryption using Anti-Circulant Matrix” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2022: 1-3.
[49] Chen Yang, Zepeng Yang, et al., “A Lightweight Full Homomorphic Encryption Scheme on Fully-Connected Layer for CNN Hardware Accelerator Achieving Security Inference” [C], Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), 2021: 1-4.
[50] Chen Yang, Siwei Xiang, et al., “A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units” [C], Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), 2021: 1-4.
[51]Chen Yang, Jia Hou, et al., “CRP: Context-Directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays” [C], Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), 2020: 1-2.
[52] Chen Yang, Xianxian Lv, et al., “MF-Conv: A Novel Convolutional Approach Using Bit-Resolution-based Weight Decomposition to Eliminate Multiplications for CNN Acceleration” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2020: 1-3.
[53] Chen Yang, Jia Hou, et al., “Hardware Trojan Attacks on the Reconfigurable Interconnections of Convolutional Neural Networks Accelerators” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2020: 1-3.
[54] Chen Yang, Bowen Li, et al., “A Fully Quantitative Scheme with Fine-grained Tuning Method for Lightweight CNN Acceleration” [C], Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), 2019: 1-2.
[55] Chen Yang, Jia Hou, et al., “CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance” [C], Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), 2019: 1-2.
[56] Chen Yang, Yizhou Wang, et al., “A Reconfigurable CNN Accelerator using Tile-by-Tile Computing and Dynamic Adaptive Data Truncation” [C], Proceedings of IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2019: 73-74.
[57] Chen Yang, Yizhou Wang, et al., “A reconfigurable accelerator based on fast Winograd algorithm for convolutional neural network in Internet of Things” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018: 1-3.
[58] Chen Yang, Haibo Zhang, et al., “An Energy-Efficient and Flexible Accelerator based on Reconfigurable Computing for Multiple Deep Convolutional Neural Networks” [C], Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018: 1-3.
[59] Chen Yang, Leibo Liu, et al., “Data Cache Prefetching via Context Directed Pattern Matching for Coarse-Grained Reconfigurable Arrays” [C], Proceedings of ACM/IEEE Design Automation Conference (DAC), 2016: 1-6.
[60] Chen Yang, Leibo Liu, et al., “Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array” [C], Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2015: 263-263.
[61] Chen Yang, Leibo Liu, et al., “Configuration Approaches to Improve Computing Efficiency of Coarse-Grained Reconfigurable Multimedia Processor” [C], Proceedings of IEEE International Conference on Field Programmable Logic and Applications (FPL), 2014: 1-4.
[62] 朱敏, 刘雷波, 尹首一, 杨晨, 王文杰, 魏少军. H.264计算密集型任务在可重构处理器上的映射. 电路与系统学报, 2013, (18)2: 366-370.
专利&软件著作权（获专利授权35项，登记软著3项）：
1. 杨晨, 席嘉蔚, 等. 一种面向基于Winograd的CNN加速器系统的数据无冲突调度方法, 2024.4.5, 中国, ZL202111178327.4
2. 杨晨, 刘依维, 等. 一种位宽可变的求模运算方法及求模运算电路, 2024.4.2, 中国, ZL202110839603.0
3. 杨晨, 王佳兴, 等. 一种基于DSP的混合位宽加速器及融合计算方法, 2023.9.26, 中国, ZL202111605030.1
4. 杨晨, 杨尧尧, 等. 面向Winograd参数可调的卷积张量优化方法及系统, 2023.9.19, 中国, ZL202110883108.X
5. 杨晨, 耿龙飞, 等. 用于图神经网络推理的动态可重构PE单元及PE阵列, 2023.9.19, 中国, ZL202110853134.8
6. 杨晨, 吕娴娴, 等. 一种Winograd卷积运算加速方法及加速模块, 2023.9.19, 中国, ZL202110588325.6
7. 杨晨, 陈琦, 等. 基于深度语义融合的卷积神经网络的三维语义图重建方法, 2023.5.2, 中国, ZL202010350966.3
8. 杨晨, 张靖宇, 等. 基于多分支卷积神经网络的行人识别方法, 2023.5.2, 中国, ZL202010345173.2
9. 杨晨, 王逸洲, 等. 一种基于长短期记忆网络的缓存替换系统及方法, 2023.4.18, 中国, ZL202010390271.8
10. 杨晨, 王逸洲, 等. 一种面向卷积神经网络加速器的Winograd卷积拆分方法, 2023.4.7, 中国, ZL201910717929.9
11. 杨晨, 陈琦, 等. 基于卷积神经网络降低单目相机位姿估计误差率的方法, 2023.3.31, 中国, ZL202010351019.6
12. 杨晨, 耿龙飞, 等. 图数据预取器及预取方法, 2023.1.10, 中国, ZL202110707805.X
13. 杨晨, 侯佳, 等. 一种基于全连接层全同态加密运算的加速器安全分类方法, 2022.12.9, 中国, ZL202110997014.5
14. 杨晨, 吕娴娴, 等. 一种按照比特精度进行权重拆分的卷积运算加速方法, 2022.12.9, 中国, ZL202011192684.1
15. 杨晨, 王佳兴, 等. 基于FPGA实现低线数光栅条件下的直流电机角度控制电路, 2022.8.9, 中国, ZL202110240848.1
16. 杨晨, 任嵩楠, 等. 一种面向同态密码运算的密钥转换方法、系统、设备及可读存储介质, 2022.4.22, 中国, ZL202010832531.2
17. 杨晨, 张靖宇, 等. 并行选取超参数设计多分支卷积神经网络识别行人的方法, 2022.4.22, 中国, ZL202010346203.1
18. 杨晨, 王逸洲, 等. 一种高吞吐率的动态可重构卷积神经网络加速器, 2022.4.22, 中国, ZL201910718678.6
19. 杨晨, 王逸洲, 等. 一种面向物联网领域的动态可重构卷积神经网络加速器架构, 2022.2.22, 中国, ZL201811149741.0
20. 杨晨, 张海波, 等. 一种用于卷积神经网络计算的动态自适应数据截断方法, 2021.9.7, 中国, ZL201910395234.3
21. 杨晨, 王逸洲, 等. 高速可重构处理器配置信息缓存替换方法及存储体系结构, 2021.9.7, 中国, ZL201911056632.9
22. 杨晨, 杨泽鹏, 等. 基于FPGA的仲裁PUF木马检测及再使用方法, 2021.9.3, 中国, ZL201910974496.5
23. 杨晨, 张海波, 等. 一种用于卷积神经网络数据存储的多bank行列交织读写方法, 2021.8.13, 中国, ZL201910395235.8
24. 杨晨, 陈琦, 等. 一种面向内存计算和室内是否有人的神经网络设计方法, 2021.7.13, 中国, ZL201910584312.4
25. 杨晨, 王逸洲, 等. 一种面向深度学习的可重构处理器运算单元, 2021.7.13, 中国, ZL201810922918.X
26. 杨晨, 张海波, 等. 一种用于卷积神经网络加速的多层数据分区域联合计算方法, 2021.4.20, 中国, ZL201910395256.X
27. 杨晨, 侯佳, 等. 一种动态可重构处理器的数据缓存预取方法, 2021.1.19, 中国, ZL201811377387.7
28. 杨晨, 刘童博, 等. 一种可重构系统的缓存分区划分方法, 2020.11.10, 中国, ZL201811377375.4
29. 杨晨, 张海波, 等. 一种用于动态可重构阵列的卷积运算数据流调度方法, 2020.7.28, 中国, ZL201811115052.8
30. 杨晨, 王逸洲, 等. 一种面向深度学习可重构处理器的片上互联结构, 2020.5.22, 中国, ZL201810877106.8
31. 刘雷波, 杨晨, 等. 以配置信息驱动数据访存模式匹配的片上缓存预取机制, 2019.1.15, 中国, ZL201610317626.4
32. 刘雷波, 杨晨, 等. 共享片上缓存划分装置, 2017.7.28, 中国, ZL201510113193.6
33. 刘雷波, 杨晨, 等. 共享片上缓存划分装置, 2017.9.22, 中国, ZL201510112753.6
34. 李树国, 杨晨. 去块效应滤波器的方法与系统, 2009.3.18, 中国, ZL200610113115.7
35. 李树国, 杨晨. 高并行度的帧内预测器的实现方法, 2008.8.20, 中国, ZL200610113868.8
36. 杨晨, 杨尧尧, 等. 基于蓝牙控制和语音识别的智能直流电机控制系统V1.0. (软件著作权登记号: 2021SR0059718)
37. 杨晨, 陈琦, 等. 基于单目视觉的三维语义地图重建系统V1.0. (软件著作权登记号: 2020SR0751070)
38. 杨晨, 张靖宇, 等. 基于目标识别和目标检测的软件V1.0. (软件著作权登记号: 2020SR0751027)
5、指导研究生和本科生情况：
主讲永利集团304am登录本科生的专业必修课《计算机原理与嵌入式系统》。已经指导完成23名硕士研究生和32名本科生的毕业论文设计工作，目前正在指导6名博士研究生、12名硕士研究生的课题研究和毕业论文工作。指导的研究生和本科生获奖情况如下：
1）永利集团304am登录校级优秀本科毕业设计论文1篇、电信学院优秀本科毕业设计论文10篇；永利集团304am登录优秀硕士学位论文3篇；研究生国家奖学金2人次
2）2024年第八届“全国大学生集成电路创新创业大赛”全国二等奖1项，西北赛区一等奖1项、二等奖1项
3）2024年“芯原杯”电路设计大赛一等奖1项
4）2023年第七届“全国大学生集成电路创新创业大赛”全国二等奖2项，西北赛区一等奖2项、二等奖2项、三等奖4项
5）2023年第十八届“中国研究生电子设计竞赛”西北赛区二等奖1项
6）2022年第十七届“中国研究生电子设计竞赛”全国三等奖1项，西北赛区一等奖1项、三等奖1项
7）2022年第六届“全国大学生集成电路创新创业大赛”全国三等奖2项，西北赛区一等奖2项、二等奖1项
8）2021年第五届“全国大学生集成电路创新创业大赛”全国三等奖1项、优秀奖1项，西北赛区二等奖1项、三等奖2项
9）2020年第二届“中国研究生机器人创新设计大赛”全国三等奖1项
10）2020年第四届“全国大学生集成电路创新创业大赛”全国优秀奖3项，西北赛区一等奖1项、二等奖1项、三等奖1项
11）2020年第十五届“中国研究生电子设计竞赛”西北赛区二等奖1项
12）2020年永利集团304am登录（2017级本科）优秀专业实习队
13）2019年 IBM OpenCAPI 异构计算设计大赛优秀奖1项
14） 2019年第三届“全国大学生集成电路创新创业大赛”全国三等奖2项，西北赛区一等奖1项、二等奖2项
15） 2019年永利集团304am登录（2016级本科）优秀专业实习队
16） 2018年第二届“全国大学生集成电路创新创业大赛”全国三等奖1项，西北赛区一等奖1项、三等奖1项
17） 2018年“中科芯杯”大学生电子设计创新创业邀请赛全国三等奖1项
18） 2018年 IBM OpenCAPI 异构计算设计大赛优秀奖1项
19） 2018年永利集团304am登录（2015级本科）优秀专业实习队
20） 2017年第一届“全国大学生集成电路创新创业大赛”全国二等奖1项
21） 2017年永利集团304am登录（2014级本科）优秀专业实习队
6、联系方式：
地址：永利集团304am登录，兴庆校区西一楼263、创新港校区4-4040
邮箱：chyang00@xjtu.edu.cn
电话：029-82663426（院办）
手机/微信：+86-13810103039
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